Many applications have large amounts of data-level parallelism and should be able to benefit from single-instruction multiple-data (SIMD) support. In SIMD execution, a single instruction operates on multiple data elements simultaneously. This is typically implemented by extending the width of various resources such as registers and arithmetic logic units (ALUs), allowing them to hold or operate on multiple data elements, respectively. However, most such applications have been initially designed as scalar processes, i.e., single-instruction single-data (SISD), configured to process one instruction and one data element at a time.
Converting scalar processes into SIMD processes (i.e., “SIMDifying”) may provide operational improvement, e.g., shortened processing times. However, a concern in such conversions is ensuring that scalar program order is preserved when necessary. Another concern is ensuring that when data is scattered into memory, the resulting vector of memory addresses includes only unique addresses (i.e., there are no duplicate addresses). Accordingly, conflict detection can facilitate such conversion.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.